1. Field of the Invention
This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to the improvement of a wiring contact portion.
2. Description of the Related Art
In MOS LSIs, the contact planarizing technique and selfalignment contact (SAC) technique for forming contact holes become more important as the integration density becomes higher.
Recently, a silicon selective epitaxial growth (SEG) technique has received much attention as a technique for simultaneously completing the above two techniques.
A conventional method for manufacturing a semiconductor device using the SEG technique is explained below with reference to FIG. 1.
First, an n.sup.+ -type source/drain diffused region 2 is formed in the surface area of a p-type semiconductor substrate 1. Then, an insulating layer 3 is formed on the substrate 1. Further, a contact hole is formed on the source/drain diffused region 2 by selectively etching the insulating layer 3. A natural oxide film (not shown) is formed on the source/drain diffused region 2. After this, the contact hole is filled with a monocrystalline silicon (Si)layer 4 having the same conductivity type (n.sup.+ -type) as the source/drain diffused region 2 by using the SEG technique. This forms an uneven surface area. Then, an Al(Aluminum) wiring layer 6 is formed on the uneven surface area including the upper area of the contact hole. Thus, the contact hole is filled with the monocrystalline silicon layer 4 and the Al wiring layer 6 is electrically connected to the source/drain diffused region 2 by using the SEG technique. With this construction, it appeared that the planarization of the contact hole and the self-alignment contact of the Al wiring layer could be attained at the same time.
However, in the fine contact of a highly integrated LSI, the width of the contact hole may be less than 1 micron so that the shape thereof may become substantially cylindrical. When the monocrystalline silicon layer is filled into the cylindrical contact hole by using the SEG technique, a plane surface or facet which is inclined with respect to the wafer surface is formed on the silicon layer. It is known that a facet with a (311) plane is formed when a Si (100) wafer is used, for example.
Therefore, as shown in FIG. 1, an upper area of the monocrystalline silicon layer cannot be fully planarized because of the presence of the facet 5 of the monocrystalline silicon layer 4 and a recess formed therein. That is, a difference in level caused by the contact hole can be improved in comparison with a case where the contact hole is not filled with the monocrystalline silicon layer 4, but it cannot be completely eliminated. Therefore, if the Al wiring layer 6 is formed under this condition, disconnection or breakage of the Al wiring layer 6 due to the difference in level may occur.
A complete planarization method for attaining a completely planarized surface, called a polycrystalline silicon selective growth technique, is known. In this case, a natural oxide(SiO) film on the source/drain diffused region is difficult to completely remove. Therefore, the SiO film is left between the polycrystalline silicon layer and the source/drain diffused region, and the resistance of the contact portion increases because of the presence of the SiO film.
As described above, the SEG technique has received much attention in the prior art, but since a facet is formed in the monocrystalline silicon layer which is filled into the contact hole using the SEG technique, the contact portion cannot be made completely flat. Further, in a case where the polycrystalline silicon layer is filled into the contact hole by using the selective growth technique, a natural oxide film cannot be completely removed, thereby increasing the resistance of the contact portion.